A microfiche appendix, which is part of the present disclosure, consists of 5 sheets of microfiche having a total of 431 frames. A paper appendix, which is part of the present disclosure, consists of one page. A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent documents or patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights.
This invention relates to programmable integrated circuits. More particularly, this invention relates to field programmable gate arrays (FPGAs) employing, e.g., antifuses.
A programmable application specific integrated circuit (ASIC) is a versatile integrated circuit chip, the internal circuitry of which may be configured by an individual user to realize a user-specific circuit. To configure a programmable ASIC, the user configures an on-chip interconnect structure of the programmable ASIC so that selected input terminals and selected output terminals of selected on-chip circuit components are electrically connected together in such a way that the resulting circuit is the user-specific circuit desired by the user. In a programmable ASIC employing, for example, amorphous silicon antifuses, selected amorphous silicon antifuses disposed between selected wire segments are xe2x80x9cprogrammedxe2x80x9d to connect the selected wire segments together electrically. Which antifuses are programmed and which antifuses are left unprogrammed determines how the circuit components are interconnected and therefore determines the resulting circuit.
A field programmable gate array (an xe2x80x9cFPGAxe2x80x9d) is one type of programmable application specific integrated circuit. For background information on field programmable gate arrays employing antifuses, see: xe2x80x9cField Programmable Gate Array Technologyxe2x80x9d edited by Stephen Trimberger, 1994, pages 1-14 and 98-170; xe2x80x9cField-Programmable Gate Arraysxe2x80x9d by Stephen Brown et al., 1992, pages 1-43 and 88-202; xe2x80x9cPractical Design Using Programmable Logicxe2x80x9d by David Pellerin and Michael Holley, 1991, pages 84-98; the 1995 QuickLogic Data Book, 1995, pages 1-5 through 2-11 and 6-3 through 6-18; the 1995 Actel FPGA Data Book And Design Guide, 1995, pages ix-xv, 1-5 through 1-34, 1-51 through 1-101, 1-153 through 1-222, and 3-1 through 4-56; U.S. Pat. No. 5,424,655 entitled xe2x80x9cProgrammable Application Specific Integrated Circuit Employing Antifuses And Methods Thereforxe2x80x9d; U.S. Pat. No. 5,825,201 entitled xe2x80x9cProgramming Architecture for a Programmable Integrated Circuit Employing Antifuses.xe2x80x9d The contents of these documents are incorporated herein by reference.
A programmable integrated circuit, such as a field programmable gate array that employs antifuses, includes a programmable interconnect structure and plurality of logic cells. The logic cells each include a number of combinatorial logic circuits, which have direct interconnections with the programmable interconnect structure, and a plurality of sequential logic element, such as D type flip-flops that act as registers. The combinatorial logic circuits may be directly connected to the programmable interconnect structure as well as connected to the input terminals of the sequential logic elements. The output terminal of one combinatorial logic circuit may be selectively coupled a plurality of the sequential logic elements as well as to directly connected to the programmable interconnect structure. Consequently, the logic cells include both combinatorial and registered connections with the programmable interconnect structure. Moreover, one of the sequential elements may selectively receive a dedicated input from the programmable interconnect structure.
In addition, the output leads of the logic cells are connected to the programmable interconnect structure through a driver that includes a protection transistor. The gate of the protection transistor is coupled to a primary charge pump, which is shared with multiple drivers. In addition, the gate of the protection transistor is coupled to a secondary charge pump that is associated with the driver.
Another aspect of the present invention is directed to a programmable device with an input/output (I/O) circuit that includes an output register coupled to the programmable interconnect structure that feeds back into the programmable interconnect structure. The I/O circuit may also include an output register and an output enable register. Where the I/O circuit includes an input register, an output register and an output enable register, a boundary scan circuitry may use the input register, an output register, and an output enable register as boundary scan registers. I/O control pads may be coupled directly to the I/O circuit, e.g., the input register, output register and the output enable register. The I/O control pads are coupled to a data terminal of a multiplexer, while the other data terminal of the multiplexer is coupled to the programmable interconnect structure. The output terminal of the multiplexer is coupled to both the programmable interconnect structure and the I/O circuit. The output register is coupled to an I/O pad through a buffer, which is controlled by the output enable register. The I/O circuit may also include a buffer with an adjustable slew rate. The buffer includes an inverter that is coupled to ground through a resistive element and through a transistor that is in parallel with the resistive element. The adjustable slew rate is controlled, e.g., by enabling or disabling the transistor that couples the inverter. Likewise, an inverter may be coupled to a voltage potential through a resistive element and another transistor that is in parallel with the resistive element. The input register may be coupled to the I/O pad through a differential translator. The differential translator, e.g., includes an input terminal that may be coupled to different voltage reference sources.
Another aspect of the present invention is directed to an FPGA with an array of logic cells that are divided into quadrant and a clock network that extends into the approximate center of each quadrant and bisects each quadrant. The clock network includes a primary clock bus that is coupled to the I/O pad, e.g., via another bus that bisects the primary clock bus, and extends horizontally between the quadrants. A plurality of second clock buses extends vertically from the primary bus into each quadrant. The clock network includes a plurality of third clock buses, each of which is coupled to one of the second clock buses and bisects a quadrant. Clock buses extend vertically, both upward and downward, from each of the third clock buses and are programmably coupled to the logic cells. The clock network may be used, e.g., to distribute a dedicated clock signal to the logic cells. In addition, a programmable phase locked loop may be used with the clock network. The phase locked loop includes a programmable divide by n circuit before the phase detector and in the feedback loop, which permits programmable control over the delay. In addition, the phase locked loop includes a programmable divide by n circuit after the voltage controlled oscillator (VCO) which advantageously extends the range of the VCO.
Another aspect of the present invention is directed to the programming architecture in an FPGA, wherein the logic cells and routing resources are divided into subsections, e.g., quadrants, with a different set of vertical programming cells and horizontal programming cells coupled to each subsection. The FPGA includes a plurality of power buses, e.g., eight, where a different set of power buses, e.g., four power buses, is coupled to each horizontal and vertical programming cells. Each set of power buses coupled to the horizontal programming cells includes at least one different power bus. The horizontal and vertical programming cells approximately bisect each subsection. Thus, the distance from the programming cells to any antifuse within a subsection is minimized. Each set of programming cells provides a subset of the power buses in one direction and another subset in the opposite direction. Thus, the FPGA includes an eight bit programming architecture.
In another aspect of the present invention, a CMOS architecture is used to program the antifuses within the FPGA. Thus, the FPGA includes at least one antifuse, a high voltage programming source switchably coupled to said antifuse and a low voltage programming source switchably coupled to said antifuse. An NMOS transistor is disposed between the high voltage programming source and the antifuse and a PMOS transistor is in parallel with the NMOS transistor. A plurality of NMOS transistors and parallel PMOS transistors may be coupled in series between the high voltage programming source and the antifuse. Likewise, an NMOS transistor is disposed between the low voltage programming source and the antifuse and a PMOS transistor is in parallel with that NMOS transistor. A control circuit provides appropriate gate voltages to the NMOS transistor and PMOS transistor to turn the transistors on and off substantially simultaneously. The use of CMOS architecture advantageously permits the gate voltage of the NMOS transistor to be approximately the same as the voltage provided by the high voltage programming source. Consequently, no charge pump is required.
This summary does not purport to define the invention. The invention is defined by the claims.